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價格:電議
所在地:上海
型號:
更新時間:2011-11-16
瀏覽次數(shù):2494
公司地址:上海市徐匯區(qū)斜土路2601號嘉匯廣場T1樓28F
錢滿意(先生)
I/O module
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FPGA chip
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# logic cells
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Standard I/O lines
|
|||
IO301
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Xilinx Virtex-II
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7k
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64 TTL
|
|||
IO302
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Xilinx Virtex-II
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7k
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32 RS422
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|||
IO303
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Xilinx Virtex-II
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7k
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16 TTL and 24 RS422
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|||
IO304
|
Xilinx Virtex-II
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7k
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32 LVDS
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|||
IO311
|
Xilinx Virtex-II
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24k
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64 TTL
|
|||
IO312
|
Xilinx Virtex-II
|
24k
|
32 RS422
|
|||
IO313
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Xilinx Virtex-II
|
24k
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16 TTL and 24 RS422
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|||
IO314
|
Xilinx Virtex-II
|
24k
|
32 LVDS
|
|||
I/O module
|
FPGA chip
|
# logic cells
|
Standard I/O lines
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Auxiliary I/O lines
(basic module) |
||
IO322
|
Xilinx Virtex-4
|
41k
|
30 RS485
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56 LVCMOS plus 4 LVDS or 32 LVDS
|
||
IO323
|
Xilinx Virtex-4
|
41k
|
16 TTL and 22 RS485
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56 LVCMOS plus 4 LVDS or 32 LVDS
|
||
IO324
|
Xilinx Virtex-4
|
41k
|
30 LVDS
|
56 LVCMOS plus 4 LVDS or 32 LVDS
|
||
IO325
|
Xilinx Virtex-4
|
41k
|
2 16-bit 105MHz A/D signals
|
56 LVCMOS plus 4 LVDS or 32 LVDS
|